From 79f7a9403e7a0037fa5b10ea66ddde626fcfa108 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Florian=20N=C3=BCcke?= Date: Thu, 17 Sep 2020 23:29:49 +0200 Subject: [PATCH] Don't write at all on bad mode instead of sneakily adjusting mode. --- src/main/java/li/cil/circuity/vm/riscv/R5CPU.java | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java b/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java index 471642dd..65cdbe97 100644 --- a/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java +++ b/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java @@ -2117,7 +2117,9 @@ public final class R5CPU implements Steppable, RealTimeCounter, InterruptControl break; } case 0x105: { // stvec, Supervisor trap handler base address. - stvec = value & ~0b10; // Don't allow reserved modes. + if ((value & 0b11) < 2) { // Don't allow reserved modes. + stvec = value; + } break; } case 0x106: { // scounteren, Supervisor counter enable. @@ -2202,7 +2204,9 @@ public final class R5CPU implements Steppable, RealTimeCounter, InterruptControl break; } case 0x305: { // mtvec Machine trap-handler base address. - mtvec = value & ~0b10; // Don't allow reserved modes. + if ((value & 0b11) < 2) { // Don't allow reserved modes. + mtvec = value; + } } case 0x306: { // mcounteren Machine counter enable. mcounteren = value & COUNTEREN_MASK;