From 8d0cef66c2c0380fa7b02a7b2ce6385d083fcd16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Florian=20N=C3=BCcke?= Date: Thu, 17 Sep 2020 22:38:25 +0200 Subject: [PATCH] Implemented actually checking TSR. --- src/main/java/li/cil/circuity/vm/riscv/R5CPU.java | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java b/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java index 30fdaddb..e5f8f574 100644 --- a/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java +++ b/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java @@ -1421,6 +1421,10 @@ public final class R5CPU implements Steppable, RealTimeCounter, InterruptControl throw new R5IllegalInstructionException(inst); } + if ((mstatus & R5.STATUS_TSR_MASK) != 0 && priv < R5.PRIVILEGE_M) { + throw new R5IllegalInstructionException(inst); + } + final int spp = (mstatus & R5.STATUS_SPP_MASK) >>> R5.STATUS_SPP_SHIFT; // Previous privilege level. final int spie = (mstatus & R5.STATUS_SPIE_MASK) >>> R5.STATUS_SPIE_SHIFT; // Preview interrupt-enable state. mstatus = (mstatus & ~R5.STATUS_SIE_MASK) | ((R5.STATUS_SIE_MASK * spie) << R5.STATUS_SIE_SHIFT);