From dbbbcbe88036d76fe3ee643581e33d2420f853d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Florian=20N=C3=BCcke?= Date: Fri, 18 Sep 2020 00:09:59 +0200 Subject: [PATCH] Made CPU non-final and allow overriding raiseException for tests. --- src/main/java/li/cil/circuity/vm/riscv/R5CPU.java | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java b/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java index cae7dd8a..edf35498 100644 --- a/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java +++ b/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java @@ -53,7 +53,7 @@ import java.util.concurrent.atomic.AtomicInteger; *
  • "C" Standard Extension for Compressed Instructions, Version 2.0
    • * */ -public final class R5CPU implements Steppable, RealTimeCounter, InterruptController { +public class R5CPU implements Steppable, RealTimeCounter, InterruptController { private static final Logger LOGGER = LogManager.getLogger(); private static final int PC_INIT = 0x1000; // Initial position of program counter. @@ -2322,7 +2322,7 @@ public final class R5CPU implements Steppable, RealTimeCounter, InterruptControl // TODO Need multiple trace lists for each combination of MPRV&MPP, SUM, MXR and priv, otherwise we have to flush traces here. } - private void raiseException(final int exception, final int value) { + protected void raiseException(final int exception, final int value) { // Exceptions take cycle. mcycle++;