From 1462fe8638331ec26436c08905325d21c645b14a Mon Sep 17 00:00:00 2001 From: Robin Randhawa Date: Wed, 27 Jan 2021 17:17:59 +0000 Subject: [PATCH] aarch64: context: Align with x86_64 code --- src/context/arch/aarch64.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/context/arch/aarch64.rs b/src/context/arch/aarch64.rs index 338e763..a8af274 100644 --- a/src/context/arch/aarch64.rs +++ b/src/context/arch/aarch64.rs @@ -1,5 +1,5 @@ use core::mem; -use core::sync::atomic::{AtomicBool, AtomicUsize, ATOMIC_BOOL_INIT, ATOMIC_USIZE_INIT, Ordering}; +use core::sync::atomic::{AtomicBool, Ordering}; use crate::device::cpu::registers::{control_regs, tlb}; use crate::syscall::FloatRegisters; @@ -8,7 +8,7 @@ use crate::syscall::FloatRegisters; /// Compare and exchange this to true when beginning a context switch on any CPU /// The `Context::switch_to` function will set it back to false, allowing other CPU's to switch /// This must be done, as no locks can be held on the stack during switch -pub static CONTEXT_SWITCH_LOCK: AtomicBool = ATOMIC_BOOL_INIT; +pub static CONTEXT_SWITCH_LOCK: AtomicBool = AtomicBool::new(false); #[derive(Clone, Debug)] pub struct Context {