Unified naming between UART and VirtIO console methods.
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@@ -133,17 +133,34 @@ public final class UART16550A implements Resettable, Steppable, MemoryMappedDevi
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return interrupt;
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}
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public boolean canReceive() {
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return receiveFifo.size() < FIFO_QUEUE_CAPACITY;
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public int read() {
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synchronized (lock) {
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if ((lsr & UART_LSR_TEMT) != 0) {
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return -1;
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}
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final byte value;
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if ((fcr & UART_FCR_FE) != 0) {
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value = transmitFifo.dequeueByte();
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if (transmitFifo.isEmpty()) {
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lsr |= UART_LSR_THRE | UART_LSR_TEMT;
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}
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} else {
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value = thr;
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lsr |= UART_LSR_THRE | UART_LSR_TEMT;
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}
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if ((lsr & UART_LSR_THRE) != 0 && !transmitInterruptPending) {
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transmitInterruptPending = true;
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interruptUpdatePending = true;
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}
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return value;
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}
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}
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public void putBreak() {
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synchronized (lock) {
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rbr = 0;
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// QEMU says: when the LSR_DR is set a null byte is pushed into the fifo.
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putByte((byte) 0);
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lsr |= UART_LSR_BI | UART_LSR_DR;
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}
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public boolean canPutByte() {
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return receiveFifo.size() < FIFO_QUEUE_CAPACITY;
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}
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public void putByte(final byte value) {
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@@ -168,29 +185,12 @@ public final class UART16550A implements Resettable, Steppable, MemoryMappedDevi
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}
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}
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public int getByte() {
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public void putBreak() {
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synchronized (lock) {
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if ((lsr & UART_LSR_TEMT) != 0) {
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return -1;
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}
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final byte value;
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if ((fcr & UART_FCR_FE) != 0) {
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value = transmitFifo.dequeueByte();
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if (transmitFifo.isEmpty()) {
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lsr |= UART_LSR_THRE | UART_LSR_TEMT;
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}
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} else {
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value = thr;
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lsr |= UART_LSR_THRE | UART_LSR_TEMT;
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}
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if ((lsr & UART_LSR_THRE) != 0 && !transmitInterruptPending) {
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transmitInterruptPending = true;
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interruptUpdatePending = true;
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}
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return value;
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rbr = 0;
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// QEMU says: when the LSR_DR is set a null byte is pushed into the fifo.
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putByte((byte) 0);
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lsr |= UART_LSR_BI | UART_LSR_DR;
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}
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}
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