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Implemented actually checking TSR.

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This commit is contained in:
Florian Nücke
2020-09-17 22:38:25 +02:00
parent d11993d3ff
commit 8d0cef66c2
1 changed files with 4 additions and 0 deletions
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4
src/main/java/li/cil/circuity/vm/riscv/R5CPU.java
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@@ -1421,6 +1421,10 @@ public final class R5CPU implements Steppable, RealTimeCounter, InterruptControl
throw new R5IllegalInstructionException(inst);
}
if ((mstatus & R5.STATUS_TSR_MASK) != 0 && priv < R5.PRIVILEGE_M) {
throw new R5IllegalInstructionException(inst);
}
final int spp = (mstatus & R5.STATUS_SPP_MASK) >>> R5.STATUS_SPP_SHIFT; // Previous privilege level.
final int spie = (mstatus & R5.STATUS_SPIE_MASK) >>> R5.STATUS_SPIE_SHIFT; // Preview interrupt-enable state.
mstatus = (mstatus & ~R5.STATUS_SIE_MASK) | ((R5.STATUS_SIE_MASK * spie) << R5.STATUS_SIE_SHIFT);