Implemented TW.

2020-09-17 22:41:59 +02:00
parent 8d0cef66c2
commit a2bc5f852c
1 changed files with 3 additions and 0 deletions
--- a/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java
+++ b/src/main/java/li/cil/circuity/vm/riscv/R5CPU.java
@@ -1467,6 +1467,9 @@ public final class R5CPU implements Steppable, RealTimeCounter, InterruptControl
        if (priv == R5.PRIVILEGE_U) {
            throw new R5IllegalInstructionException(inst);
        }
+        if ((mstatus & R5.STATUS_TW_MASK) != 0 && priv == R5.PRIVILEGE_S) {
+            throw new R5IllegalInstructionException(inst);
+        }

        if ((mip.get() & mie) != 0) {
            return false;