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Made CPU non-final and allow overriding raiseException for tests.

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This commit is contained in:
Florian Nücke
2020-09-18 00:09:59 +02:00
parent fc34c58f04
commit dbbbcbe880
1 changed files with 2 additions and 2 deletions
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4
src/main/java/li/cil/circuity/vm/riscv/R5CPU.java
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@@ -53,7 +53,7 @@ import java.util.concurrent.atomic.AtomicInteger;
* <li>"C" Standard Extension for Compressed Instructions, Version 2.0</li>
* </ul>
*/
public final class R5CPU implements Steppable, RealTimeCounter, InterruptController {
public class R5CPU implements Steppable, RealTimeCounter, InterruptController {
private static final Logger LOGGER = LogManager.getLogger();
private static final int PC_INIT = 0x1000; // Initial position of program counter.
@@ -2322,7 +2322,7 @@ public final class R5CPU implements Steppable, RealTimeCounter, InterruptControl
// TODO Need multiple trace lists for each combination of MPRV&MPP, SUM, MXR and priv, otherwise we have to flush traces here.
}
private void raiseException(final int exception, final int value) {
protected void raiseException(final int exception, final int value) {
// Exceptions take cycle.
mcycle++;